1. Field of the Invention
This invention relates to memory controllers. More particularly, this invention relates to memory controllers for providing a connection to a plurality of memory devices.
2. Description of the Prior Art
A memory controller may be provided within a data processing apparatus to provide an interface between memory addressing components of the data processing apparatus, such as a central processing unit (CPU) or a co-processor, and an external memory device which is addressable by those components. A large number of input/output (I/O) pins are usually required to provide a suitable communications interface between the memory controller and the memory device. The input/output pins can be generally grouped into a data bus for communicating data signals, which represent information content to be stored or read, an address bus for communicating address signals, which represent the location within the memory device where the information content is stored or is to be stored, and a control bus for communicating control signals for controlling the read or write operation.
There is a general requirement to provide increased bandwidth for data transfer operations to and from memory devices, and a number of memory controller configurations have been contemplated in order to meet this requirement. One possibility is to widen the memory data bus to enable an increased number of data bits to be handled by the memory controller. Another possibility is to operate a number of memory controllers in parallel. However, the use of a single, wide memory controller is inefficient unless data is being transferred in long (i.e. wide) bursts, and the use of multiple narrow memory controllers increases the memory controller pin count substantially by requiring additional address and control signal lines.